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HIP9021
PRELIMINARY
August 1996
Portable Battery Drive/Torque Controller for N-Channel MOSFETs in Motor Control Systems
Description
The HIP9021IB is a dedicated Power MOSFET driver which drives a DC motor. As a system, motor speed is controlled while controlling torque. The primary application is drive control for portable drills while providing overload protection. The main function of the HIP9021IB is to produce a pulse width modulated square wave signal which drives the gate of an N-Channel Power MOSFET. The duty-cycle is determined by the setting of an external potentiometer at the TRIGGER (speed control) input. As the TRIGGER voltage level is decreased the duty-cycle of the square wave and the speed of the motor is increased. The torque of the motor is limited by the voltage level sensed at the drain of the external Power MOSFET. When the current reaches an adjustable limit set at the TORQUE input, the drive of the Power MOSFET is disabled. The system control components include 2 adjustable potentiometer controls and 2 capacitors for the operating frequency and torque delay control. A fixed or battery supply voltage in the range of 5V to 15V may be used. The HIP9021IB is provided in a small outline plastic package for a compact surface mount to a ceramic substrate. The surface mount assembly can be fit directly into the trigger of a portable electric drill.
PKG. NO. M8.15
Features
* MOSFET Driver and DC Motor Controller * Torque Control and Overload Protection * Battery Power Supply . . . . . . . . . . . . . . . . +5V to +15V * BiMOS IC with Low Operating Current - Maximum Supply Current . . . . . . . . . . . . . . . . .1.5mA - Maximum Input Leakage Currents . . . . . . . . . . 1.5A * 500A Maximum Supply Current * 1A Maximum Input Leakage Currents * Typical Oscillator Frequency . . . . . . . . . . . . . . . . . 5kHz * Power-On-Reset Control * 10mA Drive Capability for Gate Output * Operating Temperature . . . . . . . -40oC to +85oC Range
Applications
* Portable Battery Operated Electric Drills * Controller for Small DC Electric Motors * Torque/Drive Controller for Inductive Loads * Intelligent MOSFET Drive
Ordering Information
PART NUMBER HIP9021IB TEMP. RANGE (oC) -40 to +85 PACKAGE 8 Ld SOIC
Pinout
HIP9021IB (SOIC) TOP VIEW
DRAIN TRIGGER GND OSC
1 2 3 4
8 7 6 5
VDD GATE DELAY TORQUE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
4055
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HIP9021 Block Diagram
VBATT VDD
+
DRAIN DELAY
+
TORQUE
CONTROL & LOGIC GC
TORQUE LEVEL SET TRIGGER SPEED CONTROL
+
GATE
OSC OSCILLATOR
HIP9021
GND
2
HIP9021
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16V Input Voltage. . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to VCC +0.3V Maximum Current, IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Maximum Transient Reverse Current, IR (10s). . . . . . . . . . . . -50mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only)
Operating Conditions
Typical Power Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5V Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . +5V to +15V Operating Temperature Range . . . . . . . . . . . . . . . . . -40oC to 150oC Typical Oscillator Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . 5kHz
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETER DC Supply Current OSC Source Current OSC Sink Current OSC Threshold Voltage OSC Trigger Voltage TRIGGER Input Leak Current TORQUE Input Leak Current DELAY Current at 1V DELAY Current at 2V DELAY Threshold Voltage DRAIN Input Resistance DRAIN Current GATE Output Source Current GATE Output Voltage GATE Output Slew Rate
VDD = 7.5V, Figure 1 Test Circuit, Table 1 Conditions, TA = +25oC Unless Otherwise Specified SYMBOL IDD +IOSC -IOSC VOSC(TH) VOSC(TR) ITRIGGER ITORQUE IDELAY1 IDELAY2 VDELAY(TH) RDRAIN IDRAIN IGATE VGATE VGATE(S/R) FP/DC Measured in Typical Application Circuit, Duty Cycle = 50%, See Figure 2 Gate Duty Cycle = 50%; VTORQUE = GND; VDRAIN = VGATE; DELAY =10k to GND, Refer to Figure 1 for the Test circuit and Timing Diagram of the DELAY Output Pulse Frame. TA = 25oC TA = -40oC TA = 85oC TEST CONDITIONS MIN 0.1 19 -32 4.75 2.30 1.5 1 1.8 150 1 10 6.5 TYP 1.2 25 -25 4.95 2.45 0.02 0.02 3.4 32 1.9 260 1.7 18 7.4 10 MAX 3.1 32 -19 5.25 2.65 1.5 1.5 6 50 2 350 4.6 UNITS mA A A V V A A A mA V k mA mA V V/s
DELAY Output Framed Pulse Duty Cycle DELAY Output Framed Pulse Delay, VGATE to VDELAY Typical Oscillator Frequency
-
44
-
%
FP/DLY
-
3 5 7.2 3.6
-
% kHz kHz kHz
fOSC
NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air.
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HIP9021
VDD 15K 2V 1V 2V 5V 2V 5V 5V 7.5V VDRAIN 1nF 1 DRAIN 5 + CONTROL & LOGIC GC + 7 GATE 4 OSC HIP9021 GND 3 OSC VOSC VGATE 10nF 3.75V 2.5V 5V 1nF VDD 8
+
10F
0.01F
6
VDELAY
1V 2V 10K RD
VTORQUE 1nF VTRIGGER 22nF
DELAY
TORQUE 2 TRIGGER
VGATE
VDD
GND GATE PULSE WIDTH VDELAY FRAMED PULSE WIDTH FRAMED PULSE DELAY 1V GND
NOTE: The timing diagrams relate to the delay output framed pulse and show the time duration of the delay pulse "framed" inside of the gate pulse. The framed pulse duty cycle and delay, in percent, are measured in reference to the gate pulse which is set at 50% duty cycle. The Delay output framed pulse delay is one-half of the difference of the gate pulse width minus delay output framed pulse width. FIGURE 1. ELECTRICAL CHARACTERISTICS TEST CIRCUIT FOR SIGNAL FUNCTIONS OF THE HIP9021
TABLE 1. SWITCH POSITIONS OF FIGURE 1 FOR ELECTRICAL CHARACTERISTIC TESTING SYMBOL IDD +IOSC -IOSC VOSC(TH) VOSC(TG) ITRIGGER ITORQUE IDELAY1 IDELAY2 VDELAY(TH) RDRAIN IDRAIN VGATE IGATE VGATE(S/R) FP/DC FP/DLY fOSC 1V VOSC(TH) -1V 1nF 2V GND 25K Load DRAIN 15K to 2V 15K to 2V 15K to 2V 1V 1V 15K to 2V 15K to 2V 15K to 2V 15K to 2V 1V 5V 1V 5V 2V TRIGGER GND GND GND Open Open 5V Open 7.5V 7.5V Ramp Up GND 7.5V GND GND OSC 3.75V 2.5V 5V 1nF 1nF 5V 5V 1nF 1nF 1nF 1nF 5V 1nF 1nF TORQUE 2V 2V 2V 2V 2V 2V 5V Open Open 2V 2V 2V 2V 2V DELAY Open Open Open Open Open Open Open 1V 2V GND GND Open Open GND GATE Open Open Open Open Open Open Open Open Open Read VGATE Open Open Open Set to VOUT -0.5V MEASURE IDD Current Into VDD Pin Source Current From OSC Pin Sink Current Into OSC Pin Positive Peak OSC Voltage Negative Peak OSC Voltage TRIGGER Leakage Current TORQUE Leakage Current Current to DELAY Pin Current to DELAY Pin Measure VTRIGGER When VGATE Less Than 0.5V DRAIN Current; Calculate RDRAIN = 5V/IDRAIN DRAIN Current Measure VGATE = VOUT Measure IGATE Source Current with VGATE = VOUT -0.5V GATE Output Slew Rate Reference Figure 1 Waveforms Reference Figure 1 Waveforms GATE Output Timing
Refer to Figure 2 Application Circuit, 50% GATE Output Duty Cycle
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HIP9021 Pin Descriptions
NAME DRAIN NUMBER 1 DESCRIPTION The input to the DRAIN pin senses the drain of a power MOSFET Output Motor Driver. The DRAIN voltage is an image of the current flowing through the power MOSFET. By limiting this voltage, the torque of the motor can be controlled. The TRIGGER input is an analog voltage control level used to fix the duty-cycle at the DRAIN Output. A voltage level here is determined by a potentiometer adjustment. The TRIGGER voltage level is compared with the triangle signal from the internal oscillator to produce a pulse-width modulated signal. Negative pole of the battery or system ground reference. Oscillator output normally terminated in a charge/discharge capacitor. A constant current is flowing in and out to charge and discharge the external capacitor. The TORQUE input is a reference level adjustment for torque control. The voltage reference is compared with DRAIN input. If VDRAIN > VTORQUE, the GATE output pulse drive must be disabled. An external capacitor at the DELAY output is used to delay the torque control action. The external capacitor at the DELAY pin will start to be charged if a MOSFET output over-current condition is detected. The purpose of the capacitor is to delay the disabling action of the signal GATE drive. The GATE output drives the Gate of the Power MOSFET. Positive pole of the battery or Power Supply Voltage, nominally 7.5V.
TRIGGER
2
GND OSC
3 4
TORQUE
5
DELAY
6
GATE VDD
7 8
VBATT SW 7.5V VDD 330 15K DRAIN TORQUE + CONTROL & LOGIC GC + 1nF OSC OSCILLATOR SPEED CONTROL 3.3F DELAY PORTABLE ELECTRIC DRILL MOTOR
1F
+
180K TORQUE LEVEL SET 100K 200K 5.6K 270K
470K TRIGGER
GATE
RFP45N03L N-CHANNEL POWER MOSFET 1nF
HIP9021
GND
NOTE: The value chosen for the torque level set pot is dependent on the type of power MOSFET and motor characteristics. The TRIGGER is a combined SW/Speed Control function. Motor speed increases as the TRIGGER voltage decreases. Speed control range: 2.35V (Min) < VTRIGGER < 5.25V (Max) FIGURE 2. TYPICAL OPERATING CIRCUIT SHOWING THE HIP9021IB AS AN N-CHANNEL MOSFET DRIVER IN A PORTABLE BATTERY ELECTRIC DRILL APPLICATION
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HIP9021 Functional Description
Oscillator The Oscillator triangle waveform is generated by the charge and discharge of a 1nF external capacitor connected to the OSC pin. The OSC terminal has a source and sink drive from a current mirror which delivers 25A. The charge and discharge of the external capacitor is controlled by 2 comparators which compare respectively VOSC with 2/3 VDD and VOSC with 1/3 VDD. The period of the triangle wave is nominally 200s. Gate Driver The TRIGGER input signal is compared from the triangle waveform of the oscillator to produce a square wave signal. The duty cycle of the GATE drive signal is increased as the TRIGGER input level increases. The output of the comparator is then NANDed with a GATE Control signal which can enable or disable the GATE output. The NAND gate output is buffered to deliver 18mA typical GATE drive current. Torque Effect The triangle signal, after going through a divider, is also compared with TRIGGER input level. This produces another square wave of the same period but with a duty-cycle that is smaller than the GATE by ~5%. This square wave is used to enable the comparison between DRAIN and TORQUE inputs while the MOSFET is conducting.
TORQUE VDD
A torque effect condition exists when 80% of the DRAIN signal is higher than the TORQUE input level set voltage of the potentiometer. During this time, the external delay capacitor of 3.3F is charged through an internal 100K resistor. When the voltage at the DELAY pin reaches 0.25 x VDD, the RS flip-flop is then set and the Gate Control (GC) signal shown in Figure 3 goes to low. The Output GATE drive signal is then disabled. This situation remains even if the voltage on the DELAY pin stays under 0.25 x VDD for a sustained period of time. At the same time, when the RS flip-flop is set, the external capacitor at the DELAY pin is discharged via the nMOS device, Q2 which is driven by the Q output of the flip-flop. Power-On Reset (POR) In reference to Figure 3, the power on of the chip will cause the reset of the RS Gate Control flip-flop when Q1 is switched low. As an initial condition, the Gate Control (GC) signal is reset high. Since power on is the only way to reset the RS flip-flop, a disabled GATE drive signal due to a torque effect condition requires a switched (trigger) reset. The POR (power on reset) threshold requires that VDD be less than 2V to initiate a reset. The POR circuit is based on the behavior of the voltage reference cell that produces a constant 1.15V (REF. BIAS) when VDD is over 2V. When Q1 is forward biased, the Q1 drain voltage goes low to reset the input of the RS flip-flop.
100K DELAY
+
LOAD COMP
330K
3.3F
PULL DOWN
50K
200K
REF. BIAS 1.15V Q1
150K R POR MOTOR Q Q2 VBATT
6K
+ -
2K
DELAY COMP
S
Q
GATE CONTROL (GC) DRAIN 15K
OSC TRIGGER + GATE BUF
POWER MOSFET
OSC
2K 40K
+

1nF
FIGURE 3. DETAILED LOGIC DIAGRAM OF THE PORTABLE DRIVE/TORQUE CONTROLLER FOR N-CHANNEL POWER MOSFETS SHOWING THE DRAIN AND TORQUE, THE GATE CONTROL LOGIC AND THE TRIGGER (SPEED) CONTROL.
6
HIP9021 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A A1
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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